Verification of a Multi-language Components A case Study: Specman E Env with SV UVM VIP

This poster was presented at DVCon Europe 2020, presenting a case study on multi-language verification, examining how to integrate a SystemVerilog UVM VIP with an existing Specman E verification environment. The study compares different approaches: translating code between languages, co-running both languages together, or rewriting from scratch. The research concludes that partial translation can be more efficient than full language porting for certain verification scenarios, particularly memory access sequences.