ASIC Senior DFT Engineer
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Develop/code the designed features/solutions.
Developing and implementing DFT architecture
Minimum of 5 years hands-on experience in backend flow.
This position includes hands-on SOC verification tests development for full chip, cluster, and block levels.
Responsibility for the overall design of digital logic blocks from an architectural specification, RTL design, block level verification, synthesis, timing constraints - through full-chip sign-off.
Responsibility for defining an efficient hardware u-architecture to meet varies product requirements.
Designing a new and innovative architecture of parallel computing.
Developing advanced verification solutions.
Developing advanced verification solutions
to design a new and innovative architecture of parallel computing
Developing advanced Verification solutions
to develop advanced Verification solutions
Working on new Data Center switch project
Artificial Intelligence project
for Automotive project
Course coming up... Stay tuned!
Experienced FPGA/RTL Designer
Experienced Verification Engineer
Experienced Design Engineer