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Formal Verification

Formal Verification can be used alongside with functional verification to address some difficult project challenges.

This may include complex control logic blocks or mission-critical cases where functionality must be exhaustively verified for safety and security reasons. In some other instances, the design may not be fully specified/understood/documented, so it is hard to capture all the relevant cases in a traditional verification environment. Another application is when integrating a 3rd party IP that is suspected not to be fully verified.  Above all, Formal verification doesn’t require writing a full test environment and can often provide good results in a shorter time. In summary, Formal Verification can be applied in a multitude of situations, as part of a holistic verification strategy, while offering a high cost/efficiency benefit.   And yet, in spite of its increasingly wider adoption, it’s still believed to be “magic” and many teams don’t adopt it for lack of knowledge and experience.

The Veriest Formal Verification team has accumulated a wealth of experience in Formal Verification across different projects and different EDA tools and technologies. We specialize in seamlessly introducing Formal Verification into the project flow as part of the overall verification strategy, recommending the best spots to leverage this technique, freeing the verification team to apply the traditional methods and resources where these are most needed.

From bug-hunting to full proof  –  Veriest is the very best in Formal Verification!