Veriest collaborates with MINRES on RISC-V

Veriest collaborates with MINRES on RISC-V development

Joint work will enable early development of embedded software on RISC-V cores and safety-aware platforms


Veriest Solutions, a leading international Electronics Design Services house, and MINRES Technologies, a provider of next-generation Virtual Prototype solutions announced today a collaboration framework.



Under this collaboration, the companies will work to provide services and develop Virtual Prototyping solutions for RISC-V based systems, that allow to utilize state of the art software development paradigms (e.g. test driven design, continuous integration, agile development), resulting overall in increased productivity, reduced time-to-market, and most notably in the improvement of critical embedded system quality metrics, such as functional safety and security.



Furthermore, the companies will co-develop customized design environments that enable customers to create Safety-aware RISC-V platforms, under ISO26262 standard, leveraging Veriest expertise in the ASIC design and verification domains and MINRES expertise in Virtual Prototyping and Functional Safety.



Moshe Zalcberg, CEO of Veriest, said: “RISC-V is receiving increasing attention from our international clients.  Through this collaboration with MINRES highly professional team, we will offer an extended RISC-V solution for our customers’ projects, leveraging on Veriest expertise in ASIC Design, Verification and Embedded Software”.



Eyck Jentzsch, General Manager of MINREs, added: “We are excited to collaborate with Veriest, a recognized leader in ASIC engineering services. This partnership will enable us to bring MINRES’ innovative solutions to a wider customer base”.



MINRES is a startup pioneering the development of next generation, cost-efficient Functional Safety compliant Virtual Prototyping and RISC-V IP solutions for the rapidly increasing number of safety critical embedded system applications. MINRES is a privately held company based in Munich, Germany.

MINRES will be presenting a session about “Embedded Software Development for RISC-V Based SoC” at the upcoming RISC-V Roadshow on September, 16, 2019, at Dan Tel Aviv Hotel, Israel.

For additional details, see: