Veriest at DAC 63: Five Sessions on the Future of Chip Design
Two days, five sessions, and one recurring question: where is chip design really heading?
At the 63rd Design Automation Conference, held July 27–28, 2026, Veriest took the stage in a big way. Three of our leaders chaired five sessions spanning AI across the design flow, the future of specifications, venture investment, and quantum computing. Here is a look at what we brought to DAC, and what we learned along the way.
AI beyond verification
For years, verification has been the natural home for AI in chip design. Our CEO, Eli Dagan, set out to ask what comes next.
Eli chaired Scaling AI for Chip Design: Platforms and Infrastructure, an Exhibitor Forum session on Tuesday, July 28. The session followed AI as it moves into implementation, from RTL creation and logic optimization to physical design, timing closure, emulation, and analog/mixed-signal work. Speakers were refreshingly candid about the hard parts too: deploying in production, fitting into established toolchains, and guessing where the next disruption will land.
The lineup:
- Will Salcedo on GPU-accelerated EDA for semiconductor workflows
- Ferdinando Frediani on AI-driven automation for analog and mixed-signal design
- Anna Goldie on closing the loop between AI and the hardware that powers it
- Jonathan Birjiniuk on breaking the EDA bottleneck for agentic chip design
Watch the session · Session page
From hype to real results, and better specs
Predrag Nikolic, our AI Tech Lead, chaired two sessions that came at the front end of design from different angles.
Beyond the Hype: Innovation in AI for Chip Design and Verification
On Monday, July 27, Predrag led an Exhibitor Forum session built around one practical question: where is AI delivering measurable value in verification today? The focus was on functional verification, debug, coverage closure, and testbench productivity. Speakers shared real-world lessons from bringing machine learning and generative AI into existing verification environments.
- Johann George on auto-formalization, turning specifications into verifiable hardware logic
- Shashank Chaurasia on a reasoning engine for silicon verification
- Jordon Kashanchi on AI-native workflows from architecture to production readiness
- Gadi Laufer on autonomously taking digital blocks from concept to timing constraints
Watch the session · Session page
Spec-tacular! Reinventing Design Specifications with AI
Every engineer knows the pain: specifications that are ambiguous, inconsistent, incomplete, or out of date by the time they matter. On Tuesday, July 28, Predrag chaired an Engineering Special Session on fixing that with AI.
The discussion covered catching contradictions and gaps in specs, generating specs from meeting recordings and email threads, and deriving verification plans and coverage models straight from them. It also tackled the practical challenges, such as specs too large for an LLM’s context window, diagrams that need multimodal models, and detecting spec drift over a project’s life.
Presenters included Jeremiah Crane, Mariana Shenker, Hadi Ahmadi, Jeffrey Pan, and Erfan Rostami.
Following the money, and the qubits
Our Chairman, Moshe Zalcberg, chaired two sessions that looked further out: who is funding the industry’s next chapter, and what quantum computing means for engineers today.
What Are VCs Looking for at DAC?
Chip design and EDA are going through a genuine renaissance, and investors have noticed. More and more of them now come to DAC to spot trends and meet founders. Moshe organized and moderated this DAC Pavilion panel on Tuesday, July 28, with four leading investors:
- David (Dede) Goldschmidt, Samsung Catalyst Fund
- Guru Chahal, Lightspeed
- Shahin Farshchi, Lux Capital
- Rajeev Madhavan, Radiant
The panelists shared their investment theses, the ideas they are backing, and their advice for current and aspiring founders.
Watch the panel · Session page
From Bit to Qubit: EDA Meets Quantum
On Monday, July 27, Moshe chaired an Engineering Special Session that skipped the theory and went straight to practice. The session showcased real tools, including quantum EDA platforms and digital twin solutions, and explored how quantum concepts meet today’s chip design workflows.
- Chris Mueth on quantum EDA for superconducting qubits and amplifiers
- Anastasia Marchenkova on using quantum to design better qubits
- Jonathon Riddell on capturing quantum components in quantum EDA
- Duncan Huffman on the path from quantum to software development
The big picture
Looking back, the five sessions traced the whole journey of a chip, from the first lines of a specification through verification and implementation. Along the way they touched the infrastructure that makes AI work at scale, the investors betting on the next wave, and the quantum technologies on the horizon.
One theme ran through all of it. AI is no longer a promise in chip design; it is becoming part of how real teams work. At Veriest, we are proud to help lead that conversation, and even prouder to help our customers put it into practice.
Missed us at DAC? Watch the session recordings linked above, or get in touch to talk about how AI can accelerate your next project.