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Veriest at Cadence LIVE Europe 2020

Two of Veriest’s engineers presented at Cadence LIVE Europe 2020, held as a Digital Experience in October.

On the Cadence LIVE on-demand website, you can watch Eran Lahav’s session on how to combine Specman and SystemVerilog in the same Verification environment, as well as Mihajlo Katona’s presentation about safety┬áconsiderations in Chip design.

Here are the preview videos of their presentations.