Role Description
This is a full-time hybrid role for a Formal Verification Engineer in Petach Tikva, Israel. The Formal Verification Engineer will be responsible for developing and implementing Formal Verification environments, writing and applying verification plans, and conducting formal property verification. Additional tasks include analyzing coverage results, debugging, working with design engineers to resolve issues, and reporting outcomes to ensure the accuracy and efficiency of the designs.
Qualifications
- At least 2 years of experience.
- Experience with developing and implementing Formal Verification environments and writing verification plans.
- Proficiency in Formal Property verification and debugging skills.
- Strong analytical skills and experience with coverage results analysis.
- Ability to work closely with design engineers to identify and resolve issues.
- Excellent written and verbal communication skills.
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Python scripting is a plus.
- Experience in the semiconductor industry is a plus.