July 1st 2020
Israel 5pm | CET 4pm | GMT 3pm
US ET 10am | Central 9am | PT 7am
About this event
At Veriest, we believe in knowledge sharing. At our first On-line meetup in early April, 150 professionals from 15 different countries gathered to listen to experts from Intel in Israel and ST Microelectronics in Italy.
We’re now inviting you to join our next event, with a thought-provoking keynote about HW security and an award-winning technical presentation about verification of image processing.
Looking forward to hosting you!
Speakers and Agenda
CEO, Amida, US
Some new ideas in hardware security
Consumer devices and mission-critical security systems are increasingly dependent on commercial-off-the-shelf (COTS) components. These packages typically have "excess" functionality that create vulnerabilities that can be exploited by bad actors and adversaries. Commercial hardware devices are largely manufactured or assembled in countries that lack strong trust commitments (or relationships) with buyers, including defense-related industries. Even if a sub-system is directly purchased from an allied manufacturer, the components are often manufactured and assembled in untrusted foundries. As such, the devices may contain hidden hardware or be manufactured using counterfeit components that already contain Trojan content. Without some form of security and trust verification, it is almost impossible to know if a COTS device is authentic or safe to use. In this talk, we will discuss such security challenges and some novel approaches to address them.
Axis Communications, Sweden
Verifying image processing blocks using constrained random verification involves constraining image data to exercise all relevant corner cases. For some types of algorithms, constraining individual pixels is enough. Other algorithms, which operate on blocks, may require complex dependencies among groups of pixels. Expressing such dependencies as constraints on individual pixels is cumbersome and usually places a significant burden on the constraint solver. To address this problem, we have developed a UVM-based SystemVerilog framework that supports efficient randomization of images with complex inter-pixel dependencies. This framework has successfully been applied to close coverage for several of our image processing blocks. This paper was awarded a Best-Paper award at DVcon US 2020.
Save your place!