invites you to the very best
Online Verification Meetup
September 22nd 2020
Israel 5pm | CET 4pm | GMT 3pm
US ET 10am | Central 9am | PT 7am
About this event
At Veriest, we believe in knowledge sharing. This is why we organize a series of on-line meetups attended by design & verification professionals from 15 different countries. So far, we hosted experts from Intel, ST Microelectronics, Texas Instruments, Axis Communications and other great companies.
We’re now inviting you to join our next event, with an interesting keynote about Safety in Deep Learning devices and an award-winning technical presentation about formal verification of deadlock cases.
Looking forward to having you!
On-line Event
Link to meetup will be sent upon registration
Speakers and Agenda
Keynote presentation
Principal Engineer, Intel US; IEEE Senior Member
Functional Safety and Soft Error Rate Modeling for Deep Learning Applications
Compliance to FuSa metrics and SER requirements pose challenges for safety critical systems. This talk will focus on soft error rate modeling for functional safety, with a focus on product vulnerability factors for AI and Deep Learning applications. It will describe different considerations and approaches for derating, based on workloads, and will highlight methodologies to architect and design for transient reliability and safety in the context of artificial intelligence.
Technical presentation
Sr. Principal Engineer, Arm France
Easy Deadlock Verification and Debug with Advanced Formal
* Best Paper award at DAC’2020
Deadlock bugs are the scariest bugs, and the most difficult to find.
Formal verification techniques have clear advantages over simulation-based verification techniques for finding deadlock bugs, but the traditional formal methods used in industry are difficult to apply and debug.
This presentation shows how a new formal-tool feature substantially simplifies the application of formal verification to detect deadlocks.
We applied this technique to the verification of various units in a high-performance CPU design currently under development. It allowed us to more efficiently find RTL bugs, and formal testbench bugs; and, it made the debugging task shorter and less tedious.
Closure
Q&A
Total event duration 1:15 hr
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