Verification Engineer

Requirements:

Requirements:

– BSc. In electronics /computer engineering /computer science/ physics – a must

– At least 2 years of hands-on verification experience with System Verilog UVM/VMM

– Experience with development verification environment in the system Verilog/UVM methodology – a must

– Ability to work in a dynamic environment and on several tasks

– Self-learning skills, Excellent troubleshooting skills and Self-motivated skills

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