ASIC Backend Design Engineer


  • RTL to GDS flow
  • Responsible for floor planning, physical synthesis, and physical design closure of large complex designs at various processes including sub 16nm processes.
  • Responsible for driving timing closure through physical synthesis and Place & Route tools and working with ASIC vendors.
  • Work with Frontend team to understand the RTL design and drive physical aspects early in design cycle for physical design closure.
  • Resolve design and flow issues related to physical design, identify potential solutions


  • Minimum of 5 years hands-on experience in backend flow.
  • Experience with large SoC designs and complex blocks.
  • Hands on experience in block level implementation including physical synthesis, placement, CTS, routing, and optimization using Synopsys ICC2/Cadence Innovus
  • Hands on experience in Synopsys DC/DCG or Cadence Genus.
  • Requires strong knowledge and experience of multi-clock domains, data path design, and multi-voltage design.
  • Strong knowledge and experience in Block-level and Full-chip Floor-planning and Physical verification
  • Well versed with timing constraints, STA and timing closure (Synopsys Prime Time or Cadence Tempus)
  • Experience with low power design features and flows.


BSEE is mandatory, MSEE – an advantage.

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