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Strive big and you may achieve it

Milos Mirosavljevic

Verification Team Leader at Veriest Venture Ltd

Credits: International Space Station
Credits: International Space Station

“So, what’s your next wild goal?”, CEO of the company I work at (Veriest) asked me, shortly after I had attended DVCon conference in Munich last year.

Up to that point, attending, even more so presenting at technical conferences seemed like a distant goal for me. Gradually however, I’ve managed to work towards it and I was sent to present at DVCon. Naturally, this only set the margin for my next goal even higher.

“I’ve always wanted to visit Silicon Valley. After all, isn’t it every engineer’s dream? I would like to present at CDNLive in Silicon Valley.” And that is how my tour began.

Quickly after submitting the abstract for evaluation, I have been notified that paper I am coauthor on, has been accepted to the conference. I am going to Silicon Valley!

After quite a lengthy trip I took with my wife on the West Coast prior to the conference itself, I have arrived at the destination.

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As in other conferences I presume, few buzzwords kept circling around this one as well: 5G, internet of things, machine learning, automovitve and AI. Some say the only missing one was blockchain.

 

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Local joke was going around the conference saying that in order to achieve the required latency and data speed for 5G all you have to do is to change the speed of light.

During the first day of the conference I have attended the lecture held by Cadence related to Verification throughput optimization for advanced designs. Speed of which Verification is done now days has become the key challenge of today’s and the next generation verification of System on Chips. Users need to employ smart verification practices to correct as many bugs as early as possible per dollar per day. Session highlighted the usage of new tools available today and combining a different levels of abstraction in order to do smart bug hunting.

Followed by this was the keynote session held by @Cadence CEO Lip-Bu Tan. Speech was focused on technical predictions for the future and Cadence’s intention to further enhance design and verification processes. It is interesting to say that aside verification, software developement costs are rapidly increasing up, in VLSI world (note the green line below):

 

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As the time for my presentation drew near, I was starting to get excited and slightly nervous, but not as much as prior to my first appearance last year in Munich.

 

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Session went great and I was happy to achieve the goal I set sometime ago. General conclusion is, and it is well known, that in the USA, System Verilog is much more predominant in usage, than Specman.

The next session was related to ISequenceSpecTM (ISS) tool which can be used with the Perspec, which utilizes the new Portable Stimulus Standard (PSS) to automatically generate non-redundant stimulus and coverage for verification of individual block level scenarios.

 

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Perspec is pretty trending nowdays and it was mentioned in many presentations in this conference, as well as back at DVCon.

After the first day of the conference ended, I decided to explore the Intel musem. It’s quite an amazing place, despite everything being in only one large room.

 

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The second day of the conference. For the first session I was going to attend, I picked something different than the usual, academic related. Session was related to Speech recognition with Scalp Brain signals. Speaker presented an overview of a man-machine symbiosis and an example of how this combination is better than only man or only machine. For instance, when radiologists were presented with various images, disease detection error rate was around 4.5%. Machine performed the same with 3.5% error rate. However, when combined, error rate in detection was only 2.5%. This idea was expanded in order to elaborate how speech can be detected using EEG – electroencephalography with no speech as an input. Qute an interesting topic, and it was a nice change in regard to other sessions.

Back to Verification related stuff. The next session I picked was called Transaction-level Stimulus Optimization in Functional Verification using Machine Learning Predictors. Big one, indeed. In this session the audience could hear (yet again) how Verifiction is becoming the bottleneck in the overall chip design cycle. This problem can be alleviated by the machine learning guided stimulus generation that attains verification coverage with the considerable reduction in the number of simulation cycles. Feature extraction is performed on transaction attributes, which are then fed into a machine learning model in order to predict the behavior of incomming transactions. Experimental results show reduction of about 70% coverage closure time, but this is all still heavily in a theoretic domain. Still, that’s how breakthroughts in the industry are done.

 

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Finally, I decided to visit something automotive related – Cadence’s session about the (in)famous ISO26262 standard. This standard is a Functional Safety Standard related to automotive industry. Increasing complexity throughout the automotive industry is resulting in increased efforts to provide safety-compliant systems. For example, modern automobiles use by-wire systems such as throttle-by-wire. This is when the driver pushes on the accelerator and a sensor in the pedal sends a signal to an electronic control unit. This control unit analyzes several factors such as engine speed, vehicle speed, and pedal position. It then relays a command to the throttle body. It is a challenge of the automotive industry to test and validate systems like throttle-by-wire. The goal of ISO 26262 is to provide a unifying safety standard for all automotive systems.

 

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Main issue is that the ISO 26262 is written by the automotive industry for the automotive industry, so chip manufacturers didn’t really understand what exactly should or should not be done. Edition 2 should address this. Session was about the implications of the Edition 2, which has recently been released.

 

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I would like to emphasize that all the presentations will be available for download from CDNLive website, so if you are interested in the topics I mentioned, or some others, feel free to explore.

As the conference was comming to an end, I decided to fulfill my other desire, which was to do a sight tour around Silicon Valley.

 

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Stanford Campus
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This venture reminded me of one very peculiar experience from my childhood, when it comes to setting goals. It had happened around 20 years ago, during my primary school. Each student had been scheduled to have a conversation with the school psychologist. Among many other questions, he had asked me what would I like to do when I grow up. I said that I would like to go to spaceAlbeit written in cyrillic, the highlighted part in the left picutre is this exact quote, released in a local magazine two decades ago.

Who knows, maybe by having people like Elon Musk around (yes, I’m a fan), common people, including myself, would be able to actually go to space in a not so distant future, as a part of a regular tourist atraction. For less than a million dollars, of course.

Needless to say, I am greatful to Veriest, company in which I have been for seven years now, for giving me this opportunity. And while speaking at the conference is not a dream per se, it is still a significant career goal, and is important to never stop chasing either of these two, no matter how big they are.

 

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